发明名称 Duty detection circuit
摘要 A semiconductor device includes a first duty determining circuit (20) and a second duty determining circuit (30). The first duty determining circuit (20) determines a duty correction condition for an input signal in a first predetermined cycle longer than a cycle of the input signal to obtain a first determination result and updates the duty correction condition for the input signal on the basis of the first determination result. The second duty determining circuit (30) determines the duty correction condition for the input signal in a second predetermined cycle shorter than first predetermined cycle to obtain a second determination result and updates the duty correction condition for the input signal only when the second determination result is fixed during a predetermined period.
申请公布号 US8120403(B2) 申请公布日期 2012.02.21
申请号 US20090468608 申请日期 2009.05.19
申请人 MIYANO KAZUTAKA;ELPIDA MEMORY, INC. 发明人 MIYANO KAZUTAKA
分类号 H03K3/017;H03K5/04 主分类号 H03K3/017
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