| 摘要 |
Disclosed is a dual shift register that includes a first shift register configured to include a plurality of stages which sequentially output scan pulses using at least two clock signals with sequential and circular phases, and a second shift register configured to a plurality of stages which form pair with the respective stages of the first shift register and sequentially output the scan pulses using at least two clock signals. Each stage includes: a scan direction controller configured to respond to the scan pulses from previous and next stages and to selectively output forward and reverse direction voltages with opposite electric potentials to each other; and an output portion configured to respond to the output signal of the scan direction controller, to generate two sequential scan pulses using two of the at least two clock signals, and to distribute the sequential scan pulses to the previous and next stages. |
