发明名称 LOGIC CONVERTER
摘要 FIELD: computational engineering. ^ SUBSTANCE: device contains four information inputs and three setup inputs, the vote-taking elements (11Ç17) and is performed with an option of implementation of any of five symmetrical Boolean functions depending on five arguments - input binary waveforms. ^ EFFECT: decrease in hardware costs and increasing the processing speed reached due to a decrease in the number of vote-taking elements and a decrease in the maximum signal delay time. ^ 1 dwg, 1 dwg
申请公布号 RU2443009(C1) 申请公布日期 2012.02.20
申请号 RU20110103403 申请日期 2011.01.31
申请人 ZAKRYTOE AKTSIONERNOE OBSHCHESTVO "IVLA-OPT" 发明人 ANDREEV DMITRIJ VASIL'EVICH;KUZNETSOV IGOR' ALEKSEEVICH;NOSOV SERGEJ BORISOVICH
分类号 G06F7/57 主分类号 G06F7/57
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