METHOD FOR PLANARIZING INSULATION LAYER OF SEMICONDUCTOR DEVICE

摘要

PURPOSE: A method for planarizing an insulation layer of a semiconductor device is provided to minimize the size of a pillar left in the periphery of the insulation layer by removing the insulation layer broader than the area of a pattern, and to reduce an absolute step between the upper portion and the peripheral portion of the pattern by eliminating the minimized pillar by a wet-etch process. CONSTITUTION: The insulation layer is formed on a semiconductor substrate(100) having the pattern(102) of a predetermined height. A photoresist pattern is formed on the insulation layer to expose only the planarized portion of the insulation layer in the upper portion having the pattern. A predetermined depth of the exposed planarized portion of the insulation layer is etched. The pillar formed in the inclined part of the insulation layer is eliminated by a wet-etch process. The remaining insulation layer is reflowed.