发明名称 WIRING BOARD AND SEMICONDUCTOR PACKAGE
摘要 <P>PROBLEM TO BE SOLVED: To provide a wiring board and a semiconductor package that can effectively cope with an increase in number of terminals due to high integration, acceleration and multiple functions of semiconductor devices as well as with a narrowing pitch of intervals between the terminals, and are excellent in reliability. <P>SOLUTION: In the wiring board 13 in which a lower-layer wiring composed of a wiring body 6 and an etching barrier layer 5 is formed in a concavity 7a formed on one surface of a substrate insulator film 7, an upper-layer wiring 11 is formed on the other surface of the substrate insulator film 7, and the wiring body 6 of the lower-layer wiring and the upper-layer wiring 11 are formed on the substrate insulator film 7 and are mutually connected via a via hole 10, the shape of the via hole 10 is bell-shaped. <P>COPYRIGHT: (C)2012,JPO&INPIT
申请公布号 JP2012033973(A) 申请公布日期 2012.02.16
申请号 JP20110248227 申请日期 2011.11.14
申请人 NEC CORP;RENESAS ELECTRONICS CORP 发明人 YAMAMICHI SHINTARO;KIKUCHI KATSU;MURAI HIDEYA;FUNAYA TAKUO;MAEDA TAKEHIKO;OGAWA KENTA;TSUKANO JUN;HONDA HIROKAZU
分类号 H01L23/12;H01L25/065;H01L25/07;H01L25/18 主分类号 H01L23/12
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