发明名称 |
PROCESSOR HAVING EXECUTION CORE SECTIONS OPERATING AT DIFFERENT CLOCK RATES |
摘要 |
A processor including a first execution core section clocked to perform execution operations at a first clock frequency, and a second execution core section clocked to perform execution operations at a second clock frequency which is different than the first clock frequency. The second execution core section runs faster and includes a data cache and critical ALU functions, while the first execution core section includes latency-tolerant functions such as instruction fetch and decode units and non-critical ALU functions. The processor may further include an I/O ring which may be still slower than the first execution core section. Optionally, the first execution core section may include a third execution core section whose clock rate is between that of the first and second execution core sections. Clock multipliers/dividers may be used between the various sections to derive their clocks from a single source, such as the I/O clock. |
申请公布号 |
US2012042151(A1) |
申请公布日期 |
2012.02.16 |
申请号 |
US20100879872 |
申请日期 |
2010.09.10 |
申请人 |
SAGER DAVID J.;FLETCHER THOMAS D.;HINTON GLENN J.;UPTON MICHAEL D. |
发明人 |
SAGER DAVID J.;FLETCHER THOMAS D.;HINTON GLENN J.;UPTON MICHAEL D. |
分类号 |
G06F15/76;G06F1/08;G06F9/02;G06F9/30;G06F9/38;G06F15/78 |
主分类号 |
G06F15/76 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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