HIGH-SPEED FREQUENCY DIVIDER AND PHASE LOCKED LOOP USING SAME

摘要

A frequency divider (200) includes a least significant (LS) stage (220), multiple cascaded divider stages (230-1 to 230-N), and an output stage (210). The LS stage (220) receives an input signal (201), a program bit and a first mode signal, and generates a first frequency-divided signal and an output mode signal. Each of the plurality of divider stages (230-1 to 230-N) divides the frequency of an output of an immediately previous stage by a value specified by a corresponding program bit and a corresponding mode signal. A first divider stage (230-1) in the plurality of divider stages is coupled to receive the first frequency-divided signal and to generate the first mode signal. The output stage (210) receives the output mode signal and a control signal, and generates an output signal (299) by dividing a frequency of the output mode signal by two if the control signal is at one logic level. The output stage forwards the output mode signal without division otherwise.