| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing the ON-resistance of the semiconductor device having a power transistor with a trench gate structure. <P>SOLUTION: In a power MIS/FET Q having a trench gate structure, a distance between the end (a position P1) of an interlayer insulating layer 12 on the top surface of a source semiconductor region 3 and the end (a position P2 of the outer periphery in a groove 16) of the top surface of the source semiconductor region 3 located far from the gate electrode 9E is assumed as (a), and a distance (a distance from the position P1 to a position P3 of the outer periphery in a groove 5a) of an overlapping section between the interlayer insulating layer 12 and the top surface of the source semiconductor region 3 is assumed as (b). In such a condition as described above, (a) and (b) are set so as to satisfy a formula, 0≤b≤a. By this setup, a part of a source pad SP coming into contact with the top surface of the source semiconductor region 3 is increased in area, and a distance can be made short between the source pad SP and a channel forming semiconductor region 4, so that the ON-state resistance of the power MIS/FET Q having a trench gate structure can be reduced. <P>COPYRIGHT: (C)2012,JPO&INPIT |
