发明名称 TILED PREFETCH AND CACHED DEPTH BUFFER
摘要 <P>PROBLEM TO BE SOLVED: To pipeline a prefetch mechanism that provides cache of depth tile in a 3D graphic processing. <P>SOLUTION: A prefetch mechanism can be stored in advance in cache predictively using a triangular geometric information in a previous pipeline step, thereby improving efficiency of memory bandwidth usage. A z value compression technique can be used optionally in consideration of a further reduction of electric power consumption and the memory bandwidth. <P>COPYRIGHT: (C)2012,JPO&INPIT
申请公布号 JP2012033173(A) 申请公布日期 2012.02.16
申请号 JP20110190504 申请日期 2011.09.01
申请人 QUALCOMM INC 发明人 MICHAEL HUGH ANDERSON;DAN MINGLUN CHUANG;JOFFREY SIPPY;RAJAT RAJINDER KUMAR DHAWAN
分类号 G06T15/00;G06T1/20 主分类号 G06T15/00
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