发明名称 Verification-scenario generating apparatus, verification-scenario generating method, and computer product
摘要 Hardware blocks respectively of an arbitrary access origin and an arbitrary access destination that are mutually accessible are extracted from among a plurality of hardware blocks constituting a bus system to be verified, and a path reaching from the access-origin hardware block to the access-destination hardware block is searched for. For each path found, a verification scenario is generated to verify transactions of the access-origin hardware block for a case where access to an address range assigned to the access-destination hardware block occurs, and the verification scenario is output being correlated with the path that corresponds thereto.
申请公布号 US8117573(B2) 申请公布日期 2012.02.14
申请号 US20080230110 申请日期 2008.08.22
申请人 MORIZAWA RAFAEL KAZUMITI;FUJITSU LIMITED 发明人 MORIZAWA RAFAEL KAZUMITI
分类号 G06F17/50 主分类号 G06F17/50
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