发明名称 |
Delayed decision feedback sequence estimator |
摘要 |
Disclosed is a delayed decision feedback sequence estimator comprising a delayed decision feedback sequence estimator main unit including DDFSE computing unit group including (L+M) DDFSE computing units, equal in number to a length of each of plurality of blocks into which a received data symbol sequence is divided; wherein (L+M) DDFSE computing units are connected in a pipeline configuration to execute delayed decision feedback sequence estimation of the blocks in parallel; and an edge effect detection and correction circuit that detects an edge effect due to processing the delayed decision feedback sequence estimation of the separated block and corrects a relevant bit error. |
申请公布号 |
US8116366(B2) |
申请公布日期 |
2012.02.14 |
申请号 |
US20080149157 |
申请日期 |
2008.04.28 |
申请人 |
KAWASHIMA TOSHITSUGU;HOROWITZ MARK;RENESAS ELECTRONICS CORPORATION;THE BOARD OF TRUSTEES OF THE LELAND STANFORD JUNIOR UNIVERSITY |
发明人 |
KAWASHIMA TOSHITSUGU;HOROWITZ MARK |
分类号 |
H03H7/30;H03K5/159 |
主分类号 |
H03H7/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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