| 摘要 |
To provide a plurality of write amplifiers that perform a data write operation upon memory cells and a write control circuit that controls a timing of a data write operation performed by the write amplifiers. When a data write operation using another write amplifier is requested while a data write operation using a predetermined write amplifier is performed, the write control circuit suspends the data write operation using the predetermined write amplifier. The suspended data write operation is performed again simultaneously with the data write operation using the other write amplifier. Accordingly, random column access like that of a DRAM can be realized by simple control. |
