发明名称 |
Laminated silicon gate electrode |
摘要 |
Within a method for forming a silicon layer, there is employed at least one sub-layer formed of a higher crystalline silicon material and at least one sub-layer formed of a lower crystalline silicon material. The lower crystalline silicon material is formed employing a hydrogen treatment of the higher crystalline silicon material. The method is particularly useful for forming polysilicon based gate electrodes with enhanced dimensional control and enhanced performance. |
申请公布号 |
US8115263(B2) |
申请公布日期 |
2012.02.14 |
申请号 |
US20050041178 |
申请日期 |
2005.01.24 |
申请人 |
CHEN CHIA-LIN;YAO LIANG-GI;CHEN SHIH-CHANG;TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. |
发明人 |
CHEN CHIA-LIN;YAO LIANG-GI;CHEN SHIH-CHANG |
分类号 |
H01L29/78;H01L21/20;H01L21/28;H01L21/30;H01L29/49 |
主分类号 |
H01L29/78 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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