发明名称 |
Determining timing paths within a circuit block of a programmable integrated circuit |
摘要 |
A computer-implemented method of identifying timing paths of a circuit block can include representing a circuit block including at least one bypassable component as a block diagram having a plurality of elements linked by nodes. The method can include generating a map file including a text description of each element within the block diagram, wherein the text description of each element specifies a bypass indicator for the element. The method also can include generating a plurality of sub-paths from the map file, determining timing paths from the plurality of sub-paths by selectively combining different ones of the plurality of sub-paths according to commonality of starting points and ending points of the plurality of sub-paths, and outputting the timing paths. |
申请公布号 |
US8117577(B1) |
申请公布日期 |
2012.02.14 |
申请号 |
US20090361516 |
申请日期 |
2009.01.28 |
申请人 |
VADI VASISHT M.;CHING ALVIN Y.;KUMAR SUBODH;FREEMAN RICHARD D.;MCEWEN IAN L.;HARATSARIS PHILIP R.;LUJAN JAIME D.;SCHWARZ ERIC M.;XILINX, INC. |
发明人 |
VADI VASISHT M.;CHING ALVIN Y.;KUMAR SUBODH;FREEMAN RICHARD D.;MCEWEN IAN L.;HARATSARIS PHILIP R.;LUJAN JAIME D.;SCHWARZ ERIC M. |
分类号 |
G06F17/50;G06F9/455 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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