发明名称 FAULT ANALYSIS DEVICE AND FAULT ANALYSIS METHOD
摘要 PURPOSE: A fault analysis apparatus and a fault analysis method thereof are provided to detect a fault on a layer, thereby performing fault type classification. CONSTITUTION: A fault analysis apparatus includes a layer partition part(112), a fault classification part(113), a memory part and an inter-layer combination determination part(114). The layer partition part partitions a fail bitmap for each layer by receiving the fail bitmap for each cell of a semiconductor memory. The fault classification part performs fault type classification in the fail bitmap corresponding to each layer. The memory part stores a rule for mixing fault cells of different layers as an equivalent fault type. The inter-layer combination determination part determines a matching state of a classification result from the fault classification part to the rule. The classification results which are matched to the rule are formed into a group.
申请公布号 KR20120013184(A) 申请公布日期 2012.02.14
申请号 KR20110022957 申请日期 2011.03.15
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 IIZUKA YOSHIKAZU
分类号 G01R31/28;G06F19/00;G11C29/00 主分类号 G01R31/28
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