发明名称 |
DEPLETION MODE FIELD EFFECT TRANSISTOR FOR ESD PROTECTION |
摘要 |
A field effect transistor is provided having a reduced drain capacitance per unit gate width. A gate electrode 21 (G) having a plurality of sides is formed in first-conductivity first semiconductor region 14. Drain region 18D (D) is formed inside the gate electrode, and source regions 18S (S) are formed in respective regions outside the plurality of sides in widths that do not reduce the corresponding channel widths of the drain region. The gate electrode is formed along all the plurality of sides of the drain region in order to form a transistor. |
申请公布号 |
US2012032270(A1) |
申请公布日期 |
2012.02.09 |
申请号 |
US201113274103 |
申请日期 |
2011.10.14 |
申请人 |
OKUMURA YOHICHI;MUENZ JOSEF;TEXAS INSTRUMENTS INCORPORATED |
发明人 |
OKUMURA YOHICHI;MUENZ JOSEF |
分类号 |
H01L27/088 |
主分类号 |
H01L27/088 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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