发明名称 AC COUPLED SINGLE-ENDED LVDS RECEIVING CIRCUIT COMPRISING LOW-PASS FILTER AND VOLTAGE REGULATOR
摘要 A receiving circuit is provided that can accurately detect a clock signal that has a single phase and a small amplitude. A receiving circuit includes an AC coupled circuit 22 that creates an AC coupling between a first end and a second end, a low-pass filter circuit 23, 25 that produces a third signal by applying a low-pass filtering on a second signal that is produced on the second end in response to a first signal that is applied to the first end, and a comparator 21 that inputs the second signal and the third signal.
申请公布号 WO2012017691(A1) 申请公布日期 2012.02.09
申请号 WO2011JP04474 申请日期 2011.08.05
申请人 GVBB HOLDINGS S.A.R.L.;KANAMARU, HIROKI 发明人 KANAMARU, HIROKI
分类号 H04L25/02 主分类号 H04L25/02
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