ELECTRONIC CIRCUIT AND METHOD FOR STATE RETENTION POWER GATING

摘要

A method and an electronic circuit. The electronic circuit includes a processor having a functional mode and a low power mode, said processor comprising state flip- flops and additional flip-flops; said state flip flips are arranged to store state information about a state of the processor when the processor is in the functional mode; said state flip-flops comprise non-reset flip-flops that are arranged to store at least one non-reset value when the processor exits the functional mode; a power management circuit for providing power to the processor when the processor is in the functional mode, and for preventing power from the processor when the processor is in the low power mode; a non-reset value identification module, coupled to the state flip-flops, said non-reset value identification module is arranged to identify the non-reset flip-flops and to generate non- reset information that identifies the non-reset flip-flops; and a recovery circuit, coupled to a memory module and to the state flip-flops, said recovery circuit is arranged to retrieve the non-reset information from the memory module when the processor exits the low power mode, and to provide the non-reset value only to the non-reset flip-flops that are identified by the non-reset information; and wherein said memory module is arranged to store the non-reset information when the processor is in the low power mode.