发明名称 RECEPTION CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To provide a reception circuit capable of recovering output data with a small error. <P>SOLUTION: A reception circuit includes: a phase adjustment circuit (202) for adjusting a phase of a clock signal in accordance with a phase adjustment code; a sampling circuit (112) for over-sampling data with respect to one unit interval in synchronization with the clock signal output by the phase adjustment circuit; a digital equalizer (204) for performing equalization processing on the data sampled by the sampling circuit; a clock data recovery circuit (210) for recovering output data based on the data equalized by the digital equalizer; and a control circuit (801) for designating a tracking system or a blind system. The control circuit compares an error when the tracking system is designated with an error when the blind system is designated, so as to designate the system with the smaller error. <P>COPYRIGHT: (C)2012,JPO&INPIT
申请公布号 JP2012028935(A) 申请公布日期 2012.02.09
申请号 JP20100164171 申请日期 2010.07.21
申请人 FUJITSU LTD 发明人 KIBUNE MASAYA
分类号 H04L7/02 主分类号 H04L7/02
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