| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a memory controller inputting and outputting data to/from a memory capable of appropriately adjusting timing relation among signals based on actual operation conditions. <P>SOLUTION: A controller 20 outputs a data signal DATA and a data strobe signal DQS. The data signal DATA is input to a memory I/F section 30 via an FIFO memory 110 included in an error detection section 10. A memory I/F section 30 adjusts the timing of the data signal DATA and the data strobe signal DQS and outputs the result to a memory 5, and the data signal DATA is loop-backed to the error detection section 10. The error detection section 10 compares the data signal DATA, which is loop-backed from the memory I/F section 30, and original data signal DATA corresponding to the loop-backed data signal DATA, which is output from the FIFO memory 110, by a data comparator 125. <P>COPYRIGHT: (C)2012,JPO&INPIT |
