发明名称 REFERENCE VOLTAGE CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a reference voltage circuit whose power supply rejection ratio is large even when power supply voltage is low. SOLUTION: Even when the power supply voltage of a power supply terminal 10 becomes low, an NMOS71 operates in a non-saturation state, and an output resistance ro71 of the NMOS71 becomes low, the power supply rejection ratio PSRR<SB>LF</SB>is increased as an amplification degree Ao for a differential amplifier circuit 60 is increased. Therefore, even when the minimum operation voltage of the reference voltage circuit is low, the power supply rejection ratio PSRR<SB>LF</SB>can be increased. In other words, the amplification degree Ao of the differential amplifier circuit 60 contributes to the power supply rejection ratio PSRR<SB>LF</SB>, so that the power supply rejection ratio PSRR<SB>LF</SB>is also increased as the amplification degree Ao for the differential amplifier circuit 60 is increased. COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2009048319(A) 申请公布日期 2009.03.05
申请号 JP20070212070 申请日期 2007.08.16
申请人 SEIKO INSTRUMENTS INC 发明人 IMURA TAKASHI
分类号 G05F3/24 主分类号 G05F3/24
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