| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a memory test circuit having a BIST circuit, which is, for example, capable of reducing imbalances in application of DC stress to memory cells when used in burn-in test. <P>SOLUTION: The memory test circuit includes a BIST circuit configured to execute a plurality of operation algorithms. When the BIST circuit repeats an operation according to a provided operation mode control signal (S1) and an operation mode for changing an operation algorithm is set (S2), a repeat operation control block newly sets an operation algorithm, which is executed in the BIST circuit, according to an operation algorithm setting signal while the BIST operation is repeatedly being executed (S3 to S7). <P>COPYRIGHT: (C)2012,JPO&INPIT |
