| 摘要 |
<P>PROBLEM TO BE SOLVED: To significantly improve data transfer speed while reducing hardware costs. <P>SOLUTION: A communicator chip 2 as an interface for connecting calculation nodes in parallel comprises: communication means 6 to 9; a DMA transfer sequencer 10; an on-chip router 11; and a memory 12. The DMA transfer sequencer 10 transfers a control packet to a DMA transfer sequencer which is included in an other connected communicator chip, and specifies operation of the DMA transfer sequencer. The communication means 6 to 9 that control data transfer to/from the communicator chip or a computation node includes DMA control circuits 6a to 9a. The DMA control circuits 6a to 9a provide, to the DMA transfer sequencer 10, a DMA end interruption signal indicating the completion of DMA transfer when the DMA transfer is complete. <P>COPYRIGHT: (C)2012,JPO&INPIT |
