| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide the technology which helps to increase the manufacturing yield and the quality of semiconductor products by predicting the occurrence of problems arising from planarization by a CMP process. <P>SOLUTION: Two or more chip body layouts 1 and one scribe TEG layout 2 on a single layer are synthesized in a mask image, which is then divided into meshes to find density in each mesh. Subsequently, a plurality of mesh-divided single layers are laminated and then an average laminate density of plural layers in each mesh is obtained. From the average laminate density of plural layers in each mesh, mesh coordinates of risk spots which will become defective in planarization by a CMP process are extracted. Next, the extracted mesh coordinates of risk spots are compared with spots where manufacturing defects are pointed out or information on suggested difficulty in design, whereby the cause of defect is estimated. <P>COPYRIGHT: (C)2012,JPO&INPIT |
