SEMICONDUCTOR MEMORY DEVICE HAVING PARALLEL TEST MODE

摘要

A semiconductor memory device having the parallel test mode is provided to perform the desired operation in not only the normal mode but also the parallel test mode by using the mode synchronizing the pipe input strobe signal. A strobe signal generating unit(310) produces an input-output strobe signal and a pipe input strobe signal in response to the column operation signal. A data I/O part(330) outputs the data inputted in response to the input-output strobe signal through the local input output line to the test global input output line. A data compress(350) outputs the compression result signal condensing data delivered through a plurality of test global input-output lines in response to the control signal. The first delay unit(370) delays the input-output strobe signal. The first delay unit outputs the delayed signal to the control signal. A compression result output unit(390) synchronizes the pipe input strobe signal in the control signal.