| 摘要 |
Certain aspects relate to systems and techniques for full well capacity extension. For example, a storage capacitor included in the pixel readout architecture can enable multiple charge dumps from a pixel in the analog domain, extending the full well capacity of the pixel. Further, multiple reads can be integrated in the digital domain using a memory, for example DRAM, in communication with the pixel readout architecture. This also can effectively multiply a small pixel's full well capacity. In some examples, multiple reads in the digital domain can be used to reduce, eliminate, or compensate for kTC noise in the pixel readout architecture. |
| 主权项 |
1. An imaging system comprising:
a pixel array including a plurality of photosensors; a plurality of readout circuits each for reading light integrated in one of a plurality of photosensor subsets coupled thereto, each of the plurality of photosensor subsets including at least two photosensors of the plurality of photosensors, each of the plurality of readout circuits comprising:
a plurality of storage capacitors, each of the plurality of storage capacitors in communication with one corresponding photosensor of a photosensor subset and having capacitance for storage of an accumulated charge representing a plurality of charge dumps from the corresponding photosensor, each of the plurality of charge dumps comprising a charge representing the light integrated in the corresponding photosensor during an integration period;a plurality of timing circuits, each one of the plurality of timing circuits associated with a corresponding one of the plurality of storage capacitors, each one of the plurality of timing circuits configured for controlling a number and timing of the plurality of charge dumps to the corresponding one of the plurality of storage capacitors from the corresponding photosensor;a floating diffusion node in communication with each of the plurality of storage capacitors such that each of the plurality of storage capacitors can transfer the accumulated charge held therein through the floating diffusion node;a source follower amplifier for receiving the accumulated charge from the floating diffusion node and converting the accumulated charge into an electrical signal, the floating diffusion node and source follower amplifier shared among the photosensor subset; an analog to digital converter in communication with the source follower amplifier to receive the electrical signal representing the accumulated charge from the source follower amplifier and convert the electrical signal representing the accumulated charge into a digital signal representing the accumulated charge; a memory configured to store the digital signal representing the accumulated charge; and a noise compensation module configured to at least, for each digital signal readout,
perform a first read of the pixel array, the first read representing a kTC noise value determined, for each timing circuit of the plurality of timing circuits of each readout circuit of the plurality of readout circuits, at least partly by
turning the timing circuit on to connect the corresponding one of the plurality of storage capacitors in series with the floating diffusion node of the readout circuit, andreading a reset noise level of at least the corresponding one of the plurality of storage capacitors, the timing circuit, and the floating diffusion node of the readout circuit;perform a second read of the pixel array, the second read including the digital signal representing the accumulated charge, the noise compensation module configured to use the first read to reduce effects of kTC noise on the digital signal, andstore the first read and the second read in the memory. |
