SEMICONDUCTOR MEMORY DEVICE FOR STABLY READING AND WRITING DATA

摘要

In a semiconductor memory device, static memory cells are arranged in rows and columns, word lines correspond to respective memory cell rows, and word line drivers drive correspond to word lines. Cell power supply lines correspond to respective memory cell columns and are coupled to cell power supply nodes of a memory cell in a corresponding column. Down power supply lines are arranged corresponding to respective memory cell columns, maintained at ground voltage in data reading and rendered electrically floating in data writing. Write assist elements are arranged corresponding to the cell power supply lines, and according to a write column instruction signal for stopping supply of a cell power supply voltage to the cell power supply line in a selected column, and for coupling the cell power supply line arranged corresponding to the selected column at least to the down power supply line on the corresponding column.

主权项

1. A semiconductor device comprising:
a plurality of static memory cells (MC, MC) arranged in rows and columns, each memory cell including an access transistors (NQ3, NQ4), drive transistors (NQ1, NQ2) and load transistors (PQ1, PQ2) and for storing data therein; a plurality of word lines (WL0,WL1), arranged corresponding to the respective memory cell rows, each coupled to gates of the access transistors in the corresponding memory cells in a corresponding memory cell row; a plurality of word line drivers (WDR0, WDR1) coupled to the plurality of word lines, respectively, for driving one of the plurality of word lines to a selected state according to a word line select signal; a plurality of pairs of data lines (BL0, /BL0, BL1, /BL1), arranged corresponding to the respective memory cell columns, each coupled to source-drain paths of the access transistors in the corresponding memory cells in a corresponding memory cell column; a plurality of power supply lines (PVLA,PVLA), arranged individually and corresponding to the respective memory cell columns, each coupled to cell power supply nodes of the memory cells in a corresponding column; and read assist circuitry (100, PD, PD) for lowering a voltage level of the corresponding word line arranged corresponding to the memory cells in a selected row in data reading; write assist circuitry (108) for lowering a voltage level of the corresponding power supply line arranged corresponding to the memory cells in a selected column in data writing.