发明名称 MEMORY DEVICE AND SEMICONDUCTOR DEVICE INCLUDING MEMORY DEVICE
摘要 A memory cell retains (N−1)-bit data (N is an integer of more than 1) and an error detection bit. The memory cell has 2N data states A_1 to A_2N. Error detection bits for the data states A_i (i is 1 and an even number more than or equal to 4 and less than or equal to 2N) among the 2N data states are assigned “1” (normal), and the error detection bits for the other data states are assigned “0” (abnormal). The memory cell is brought to have the state A_i by a writing operation. During a reading operation, the error detection bit is not read out from the memory cell. The error detection bit together with the (N−1)-bit data is read out for refresh. If the error detection bit is “0”, refresh for bringing the error detection bit back to data state with the error detection bit “1” is performed.
申请公布号 US2016172021(A1) 申请公布日期 2016.06.16
申请号 US201514962472 申请日期 2015.12.08
申请人 Semiconductor Energy Laboratory Co., Ltd. 发明人 ISHIZU Takahiko
分类号 G11C11/4096;G11C11/24 主分类号 G11C11/4096
代理机构 代理人
主权项 1. A memory device comprising: a memory cell; and a circuit, wherein the memory cell is configured to retain 1-bit data of “0” or “1”, wherein the memory cell is in any of four data states, the four data states being a state A_1, a state A_2, a state A_3, and a state A_4, wherein V_1, V_2, and V_3 are voltages, wherein a threshold level of the state A_1 is lower than V_1, wherein a threshold level of the state A_2 is higher than V_1 and lower than V_2, wherein a threshold level of the state A_3 is higher than V_2 and lower than V_3, wherein a threshold level of the state A_4 is higher than V_3, wherein the circuit is electrically connected to the memory cell so as to write 1-bit data into the memory cell and read out 1-bit data from the memory cell, wherein the circuit is configured to: bring the memory cell into the state A_1 at the time of writing “0” into the memory cell and bring the memory cell into the state A_4 at the time of writing “1” into the memory cell;make a first determination whether a threshold of the memory cell is lower than V_1,make a second determination whether the threshold of the memory cell is lower than V_2,make a third determination whether the threshold of the memory cell is lower than V_3,make the second determination and read out 1-bit data from the memory cell,make the first to third determinations and, when the memory cell is in the state A_2, bring the memory cell into the state A_1, andmake the first to third determinations and, when the memory cell is in the state A_3, bring the memory cell into the state A_4.
地址 Atsugi-shi JP