发明名称 Data processing system and method with peripheral configuration information error detection
摘要 In a data processing system (101) including a first master (103) operably coupled to a peripheral bus interface and a plurality of peripherals (125, 137, 129, 133) operably coupled to the peripheral bus interface, wherein the first master communicates with each of the plurality of peripherals via the peripheral bus interface (113), a method includes initiating a write, by the first master, of configuration information to a first peripheral of the plurality of peripherals. In response to initiating the write, the configuration information is provided via the peripheral bus interface for storage into the first peripheral, wherein a first error syndrome of the configuration information is generated by the peripheral bus interface. The provided configuration information is stored in the first peripheral, and the first error syndrome is stored in storage circuitry of the peripheral bus interface. The first error syndrome can be used to check the integrity of configuration information during subsequent error checking.
申请公布号 EP2416248(A1) 申请公布日期 2012.02.08
申请号 EP20110171392 申请日期 2011.06.24
申请人 FREESCALE SEMICONDUCTOR, INC. 发明人 MILLER, GARY L.
分类号 G06F11/10;G06F11/07;G06F21/00 主分类号 G06F11/10
代理机构 代理人
主权项
地址
您可能感兴趣的专利