发明名称 |
Method and system product for implementing uncertainty in integrated circuit designs with programmable logic |
摘要 |
Disclosed is a method, system and computer program product to specify an integrated circuit. The integrated circuit includes a hardwired specific logic technology portion and a programmable specific logic technology portion. The method includes generating a hybrid logic network by mapping each uncertain logic function to an abstract programmable logic element implementation thereof and by mapping each known logic function to a technology-independent logic element implementation thereof; simplifying the hybrid logic network using logic synthesis optimizations; mapping the simplified hybrid logic network to a specific technology by mapping the abstract programmable logic element implementation to the specific programmable logic technology and the technology-independent logic element implementation to the specific logic technology; and further includes optimizing the mapped network to meet performance constraints. Generating involves using integrated circuit specification language extensions that include an Uncertain Function that is used in place of a logic function or operator, an Uncertain Function Assertion for imposing at least one constraint on the Uncertain Function, an Uncertain Register for a register having a programmable size within a specified range and an Uncertain Constant. |
申请公布号 |
US8112727(B2) |
申请公布日期 |
2012.02.07 |
申请号 |
US20080137628 |
申请日期 |
2008.06.12 |
申请人 |
DARRINGER JOHN A;DOERRE GEORGE W;KRAVETS VICTOR N;INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
DARRINGER JOHN A;DOERRE GEORGE W;KRAVETS VICTOR N |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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