发明名称 |
Semiconductor device having a plurality of shallow wells |
摘要 |
There is provided a technology which allows improvements in manufacturing yield and product reliability in a semiconductor device having a triple well structure. A shallow p-type well is formed in a region different from respective regions in a p-type substrate where a deep n-type well, a shallow p-type well, and a shallow n-type well are formed. A p-type diffusion tap formed in the shallow p-type well is wired to a p-type diffusion tap formed in a shallow n-type well in the deep n-type well using an interconnection in a second layer. The respective gate electrodes of an nMIS and a pMIS each formed in the deep n-type well are coupled to the respective drain electrodes of an nMIS and a pMIS each formed in the substrate using an interconnection in a second or higher order layer. |
申请公布号 |
US8110878(B2) |
申请公布日期 |
2012.02.07 |
申请号 |
US201113179163 |
申请日期 |
2011.07.08 |
申请人 |
MORINO NAOZUMI;HIRAIWA ATSUSHI;OKU KAZUTOSHI;ITO TOSHIAKI;IGARASHI MOTOSHIGE;SASAKI TAKAYUKI;SUGIYAMA MASAO;YANAGITA HIROSHI;WATARAI SHINICHI;RENESAS ELECTRONICS CORPORATION |
发明人 |
MORINO NAOZUMI;HIRAIWA ATSUSHI;OKU KAZUTOSHI;ITO TOSHIAKI;IGARASHI MOTOSHIGE;SASAKI TAKAYUKI;SUGIYAMA MASAO;YANAGITA HIROSHI;WATARAI SHINICHI |
分类号 |
H01L29/76;H01L23/62;H01L27/01;H01L27/12;H01L29/94;H01L31/0392;H01L31/062;H01L31/113;H01L31/119 |
主分类号 |
H01L29/76 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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