发明名称 |
Processor, method and computer program product for fast selective invalidation of translation lookaside buffer |
摘要 |
A processor including a microarchitecture adapted for invalidating mapping of at least one logical address to at least one absolute address, includes: at least one translation lookaside buffer (TLB) and a plurality of copies thereof; logic for independent indexing of each copy of the TLB; a plurality of comparators, each comparator associated with a respective output of each TLB set output for each TLB port, wherein each of the comparators is adapted for identifying mappings for invalidation; and logic for invalidating each identified mapping. A method and a computer program product are provided. |
申请公布号 |
US8112174(B2) |
申请公布日期 |
2012.02.07 |
申请号 |
US20080036398 |
申请日期 |
2008.02.25 |
申请人 |
HSIEH JONATHAN T.;SHUM CHUNG-LUNG KEVIN;WEBB CHARLES F.;INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
HSIEH JONATHAN T.;SHUM CHUNG-LUNG KEVIN;WEBB CHARLES F. |
分类号 |
G06F12/10 |
主分类号 |
G06F12/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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