| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide an all digital phase locked loop capable of correctly transmitting change in frequency difference to a DCO and reducing glitch noise. <P>SOLUTION: In an all digital phase locked loop 90 according to an embodiment, a digital frequency comparator 1, a glitch generation period detection circuit 2, a glitch compensation circuit 3, an accumulator 4, a loop filter 5, and a DCO 6 are provided. In the digital frequency comparator 1, an integer part frequency difference generation circuit 11, a decimal part frequency difference generation circuit 12, and an adder 13 are provided. The glitch generation period detection circuit 2, to which a TDC output signal Stdco output from the decimal part frequency difference generation circuit 12 is input, creates a glitch generation period signal Sgctim. The glitch compensation circuit 3, to which a frequency difference signal Sfdif and the glitch generation period signal Sgctim output from the adder 13 is input, performs, when the glitch generation period signal Sgctim is in an enable state, reduction processing of glitch noise contained in the frequency difference signal Sfdif. <P>COPYRIGHT: (C)2012,JPO&INPIT |
