| 摘要 |
A processor core includes one or more cache memories and a repair unit. The repair unit may repair locations in the cache memories identified as having errors during an initialization sequence. The repair unit may further cause information corresponding to the repair locations to be stored within one or more storages. In response to initiation of a power-down state of a given processor core, the given processor core may execute microcode instructions that cause the information from the one or more storages to be saved to a memory unit. During a recovery of the given processor core from the power-down state, the processor core may execute additional microcode instructions that cause the information to be retrieved from the memory unit, and saved to the one or more storages. The repair unit may restore repairs to the locations in the cache memories using the information.
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