发明名称 DUAL SYSTEM ARITHMETIC PROCESSING UNIT AND DUAL SYSTEM ARITHMETIC PROCESSING METHOD
摘要 <P>PROBLEM TO BE SOLVED: To provide a dual system arithmetic processing unit and a dual system arithmetic processing method, which enable automatic restoration using immediately preceding normal arithmetic data by means of a memory verification controller retry function when comparative mismatching between two systems occurs due to a temporary disturbance. <P>SOLUTION: The dual system arithmetic processing unit comprises: CPUs 21 and 22 constituting the dual system; buses 29a and 29b for transmitting arithmetic data of the respective CPUs 21 and 22 of the systems on the basis of a bus cycle; dual system storage devices 24 and 25 for storing the respective arithmetic data of the systems; and a verification logic part 23 for comparing the arithmetic data of the systems. The respective storage devices 24 and 25 of the systems are provided with: a regular area for storing the arithmetic data; and a save area for receiving the arithmetic data, for which comparative matching between the systems has been verified, from the regular area and storing it. The verification logic part 23 includes a retry function with which, when comparative mismatching between the systems occurs, the arithmetic data is read from the save area in each system and the CPUs 21 and 22 perform arithmetic operation again. <P>COPYRIGHT: (C)2012,JPO&INPIT
申请公布号 JP2012022429(A) 申请公布日期 2012.02.02
申请号 JP20100158521 申请日期 2010.07.13
申请人 HITACHI LTD 发明人 KATO SHOHEI;SHIMA YOSUKE;INADA MAMORU
分类号 G06F11/18;G05B9/03 主分类号 G06F11/18
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