| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a designing device and designing method of a semiconductor integrated circuit for reducing power consumption at scan test while suppressing increase in the circuit scale. <P>SOLUTION: An object extraction unit 102 extracts an object circuit part to be evaluated for its activation state among a combined circuit. A reduction amount calculation unit 104 calculates reduction amount of power consumption in each scan flip flop by fixing each output signal of the scan flip flop to be input to the combined circuit one by one. An evaluation unit 108 selects a scan flip flop providing the maximum reduction amount of power consumption when the output signal of the scan flip flop is fixed based on the calculation result. A fixation information storage unit 106 stores fixation information, and the object extraction unit 102 extracts an object circuit part to be evaluated based on the fixation information. The evaluation unit 108 selects a scan flip flop for each selected circuit part, and repeats this process until the total of the amount of reduction of power consumption reaches a prescribed value. <P>COPYRIGHT: (C)2012,JPO&INPIT |
