Clock generator for generating output clock having non-harmonic relationship with input clock and related clock generating method thereof

摘要

One clock generator (100, 200, 400, 600) includes an oscillator block (102, 202, 402, 602), a delay circuit (104, 204, 404, 604), and an output block (106, 206, 406, 606). The oscillator block (102, 202, 402, 602) provides a first clock of multiple phases. The delay circuit (104, 204, 404, 604) delays at least one of said multiple phases of said first clock to generate a second clock of multiple phases. The output block (106, 206, 406, 606) generates a third clock by selecting signals from said multiple phases of said second clock, wherein said third clock has non-harmonic relationship with said first clock.