发明名称 Packet coalescing in virtual channels of a data processing system in a multi-tiered full-graph interconnect architecture
摘要 A mechanism is provided for packet coalescing in virtual channels of a data processing system. A first processor bundles original data into a data packet to be transmitted to a destination processor, the original data comprising payload data and overhead data. The first processor transmits the data packet to a second processor along a path to the destination processor. The second processor determines if the second processor has additional payload data destined for the same destination processor. Responsive to the second processor having the additional payload data, the second processor unbundles the data packet, adds the additional payload data to the payload data, and rebundles the payload data along with the additional payload data and the overhead data into a rebundled data packet. Then the second processor transmits the rebundled data packet to at least one other processor along the path to the destination processor.
申请公布号 US8108545(B2) 申请公布日期 2012.01.31
申请号 US20070845227 申请日期 2007.08.27
申请人 ARIMILLI LAKSHMINARAYANA B.;ARIMILLI RAVI K.;RAJAMONY RAMAKRISHNAN;INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 ARIMILLI LAKSHMINARAYANA B.;ARIMILLI RAVI K.;RAJAMONY RAMAKRISHNAN
分类号 G06F15/16;G06F15/173;H04L1/18;H04L12/43 主分类号 G06F15/16
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