发明名称 High voltage tolerant metal-oxide-semiconductor device
摘要 A method for increasing a voltage tolerance of a MOS device having a first capacitance value associated therewith is provided. The method includes the steps of: connecting at least a first capacitor in series with the MOS device, the first capacitor having a first capacitance value associated therewith, the first capacitor having a first terminal coupled to a gate of the MOS device and a second terminal adapted to receive a first signal; and adjusting a ratio of the first capacitance value and a second capacitance value associated with the MOS device such that a second signal present at the gate of the MOS device will be an attenuated version of the first signal. An amount of attenuation of the first signal is a function of the ratio of the first and second capacitance values.
申请公布号 US8105912(B2) 申请公布日期 2012.01.31
申请号 US201113149122 申请日期 2011.05.31
申请人 HARRIS EDWARD B.;AGERE SYSTEMS INC. 发明人 HARRIS EDWARD B.
分类号 H01L21/329 主分类号 H01L21/329
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