| 摘要 |
A battery controller 10 outputs a voltage sampling and holding command signal to an integrated circuit CCn located at an upstream end of cascade connection of integrated circuits CC1-CCn such that integrated circuits CC1-CCn sample and hold output voltages of unit cells 1 grouped into battery modules M1-Mn. The battery controller 10, after confirming that the voltage sampling and holding command signal has been transmitted to an integrated circuit CC1 located at a downstream end of the cascade connection, outputs a transmission command signal to the integrated circuit CCn at the upstream end of the cascade circuit to transmit output voltages of the unit cells 1 held in the integrated circuits CC1-CCn to the battery controller 10. As a result, a time lag in the detection timings of output voltages of the unit cells 1 of the battery modules M1-Mn can be decreased. |
