发明名称 |
Structure for implementing dynamic refresh protocols for DRAM based cache |
摘要 |
A hardware description language (HDL) design structure embodied on a machine-readable data storage medium includes elements that when processed in a computer aided design system generates a machine executable representation of a device for implementing dynamic refresh protocols for DRAM based cache. The HDL design structure further includes a DRAM cache partitioned into a refreshable portion and a non-refreshable portion; and a cache controller configured to assign incoming individual cache lines to one of the refreshable portion and the non-refreshable portion of the cache based on a usage history of the cache lines; wherein cache lines corresponding to data having a usage history below a defined frequency are assigned by the controller to the refreshable portion of the cache, and cache lines corresponding to data having a usage history at or above the defined frequency are assigned to the non-refreshable portion of the cache. |
申请公布号 |
US8108609(B2) |
申请公布日期 |
2012.01.31 |
申请号 |
US20080126499 |
申请日期 |
2008.05.23 |
申请人 |
BARTH JOHN E.;EMMA PHILIP G.;HEDBERG ERIK L.;HUNTER HILLERY C.;SANDON PETER A.;SRINIVASAN VIJAYALAKSHMI;TRAN ARNOLD S.;INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
BARTH JOHN E.;EMMA PHILIP G.;HEDBERG ERIK L.;HUNTER HILLERY C.;SANDON PETER A.;SRINIVASAN VIJAYALAKSHMI;TRAN ARNOLD S. |
分类号 |
G06F12/00 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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