Example embodiments are directed to a memory chip array including a plurality of cell arrays and at least one predecoder commonly connected to the plurality of cell arrays, wherein the memory chip array promotes an efficient arrangement structure of the memory chip array and is minimized in area.
申请公布号
US8107312(B2)
申请公布日期
2012.01.31
申请号
US20080213121
申请日期
2008.06.16
申请人
PARK JAE-CHUL;KWON KI-WON;KIM CHUNG-JUNG;KIM SANG-WOOK;KIM SUL-IL;SAMSUNG ELECTRONICS CO., LTD.;SUNGKYUNKWAN UNIVERSITY FOUNDATION FOR CORPORATE COLLABORATION
发明人
PARK JAE-CHUL;KWON KI-WON;KIM CHUNG-JUNG;KIM SANG-WOOK;KIM SUL-IL