| 摘要 |
A circuit for generating an output enable signal includes a reset signal generator for synchronizing a reset signal with an external clock signal to generate an output enable (OE) reset signal, synchronizers for synchronizing the OE reset signal with an internal clock signal to generate a source reset signal, and an output enable signal output unit, reset by the source reset signal, for counting pulses of the external clock signal and the internal clock signal to output an output enable signal corresponding to a read command and CAS latency. |
