发明名称 |
Processor architectures for enhanced computational capability and low latency |
摘要 |
A processor includes a compute array comprising a first plurality of compute engines serially connected along a data flow path such that data flows between successive compute engines at successive times. The first plurality of compute engines includes an initial compute engine and a final compute engine. The data flow path includes a recirculation path connecting the final compute engine to the initial compute engine with no compute engine therebetween. |
申请公布号 |
US8108653(B2) |
申请公布日期 |
2012.01.31 |
申请号 |
US20100701090 |
申请日期 |
2010.02.05 |
申请人 |
LERNER BORIS;GARDE DOUGLAS;ANALOG DEVICES, INC. |
发明人 |
LERNER BORIS;GARDE DOUGLAS |
分类号 |
G06F15/80;G06F15/82 |
主分类号 |
G06F15/80 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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