发明名称 CLOCK-SYNCHRONIZED METHOD FOR UNIVERSAL SERIAL BUS (USB)
摘要 A clock-synchronized method for universal serial bus (USB) is described. The method includes the following steps of: (a) a transmitter sends a periodic signal to a host unit during a first time interval; (b) the host unit transmits a first equalization training sequence signal to a receiver during a second time interval to train the receiver and the transmitter continuously sends the periodic signal to the host unit; (c) a clock and data recovery device extracts the first equalization training sequence signal during the second time interval to generate a extracted clock signal and a data signal; and (d) the transmitter sends a second equalization training sequence signal to the host unit based on the extracted clock signal during the third time interval to train the host unit and the receiver and the transmitter commonly utilize the extracted clock signal as a reference clock.
申请公布号 US2012020404(A1) 申请公布日期 2012.01.26
申请号 US20100853636 申请日期 2010.08.10
申请人 HSIEH JIUN-CHENG;LIN YING-CHEN;GENESYS LOGIC, INC. 发明人 HSIEH JIUN-CHENG;LIN YING-CHEN
分类号 H04L7/00;H04L27/01 主分类号 H04L7/00
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