发明名称 REAL-TIME ERROR DETECTION BY INVERSE PROCESSING
摘要 Processors, microprocessors and logical block systems and methods, error detection systems and methods, and integrated circuits are disclosed. In an embodiment, a logic-based computing system includes a first processing core; a second processing core generated from the first processing core and including an inverted logical equivalent of the first processing core such that an output of the second processing core is a complement of an output of the first processing core; and comparator logic coupled to receive the outputs of the first and second processing cores as inputs and provide an error output if the output of the second processing core is not the complement of the output of the first processing core.
申请公布号 US2012023389(A1) 申请公布日期 2012.01.26
申请号 US20100839503 申请日期 2010.07.20
申请人 BREWERTON SIMON;HASTIE NEIL 发明人 BREWERTON SIMON;HASTIE NEIL
分类号 G06F7/02 主分类号 G06F7/02
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