发明名称 |
SEMICONDUCTOR WAFER AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE |
摘要 |
A semiconductor wafer in which a plurality of regions, designed to become semiconductor chips are provided in a matrix array with interposition of a dicing line(s) respectively separating the regions. The semiconductor wafer comprises: a plurality of test pads provided in an area(s) of the semiconductor wafer disposed between the semiconductor chips, inclusive of the dicing line(s); an inter-test pad interconnect(s) provided in parallel with the test pads in the area(s) of the semiconductor wafer disposed between the regions to become semiconductor chips; the inter-test pad interconnect(s) being connected to the test pads; and an inter-chip interconnect that interconnects at least two of the regions designed to become semiconductor chips; the inter-test pad interconnect being electrically connected to the inter-chip interconnect.
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申请公布号 |
US2012018726(A1) |
申请公布日期 |
2012.01.26 |
申请号 |
US201013258884 |
申请日期 |
2010.03.23 |
申请人 |
NAKAGAWA YOSHIHIRO;NOSE KOICHI;NOGUCHI KOICHIRO;TAGO MASAMOTO;UCHIDA SHINICHI;SATO YOSHIYUKI;NEC CORPORATION AND RENESAS ELECTRONICS CORPORATION |
发明人 |
NAKAGAWA YOSHIHIRO;NOSE KOICHI;NOGUCHI KOICHIRO;TAGO MASAMOTO;UCHIDA SHINICHI;SATO YOSHIYUKI |
分类号 |
H01L23/48;H01L21/768 |
主分类号 |
H01L23/48 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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