发明名称 |
IMPLEMENTING TIMING PESSIMISM REDUCTION FOR PARALLEL CLOCK TREES |
摘要 |
A computer-implemented method, system, and computer program product are provided for implementing timing pessimism reduction for parallel clock trees. A common path tracing algorithm in a static timing tool is enhanced to include a proximity credit used for pairs of gates in two clock trees that are placed in close proximity to each other. The proximity credit given is equal to a predefined fraction of a proximity component of a gate delay. |
申请公布号 |
US2012023469(A1) |
申请公布日期 |
2012.01.26 |
申请号 |
US20100841384 |
申请日期 |
2010.07.22 |
申请人 |
DARSOW CRAIG M.;HELVEY TIMOTHY D.;INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
DARSOW CRAIG M.;HELVEY TIMOTHY D. |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|