| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a semiconductor device in which an interlaced to progressive (IP) conversion circuit is integrated thereon so as to reduce a chip area. <P>SOLUTION: A write control regulation circuit 31 generates a write control signal so that writing video data in 1 port SRAMs 22, 23 is performed at a rate of once every four cycles of read-out clock. A read-out control regulation circuit 34 generates a read-out control signal so that reading out video data from the 1 port SRAMs 22, 23 is performed at a rate of once every two cycles of read-out clock. When writing video data in the 1 port SRAMs 22, 23 and reading out video data from the 1 port SRAMs 22, 23 simultaneously are performed, a selector 38 selects and outputs a write control signal delayed by a delay circuit 35. Therefore a 2 ports SRAM can be replaced with the 1 port SRAMs 22, 23, and a chip area of the IP conversion circuit can be reduced. <P>COPYRIGHT: (C)2012,JPO&INPIT |
