发明名称 |
Methods for Avoiding Parasitic Capacitance in an Integrated Circuit Package |
摘要 |
An integrated circuit package substrate includes a first and an additional electrically conductive layer separated from each other by an electrically insulating layer, a contact pad formed in the first electrically conductive layer for making a direct connection between the integrated circuit package substrate and a printed circuit board, and a cutout formed in the additional electrically conductive layer wherein the cutout encloses an area that completely surrounds the contact pad for avoiding parasitic capacitance between the additional electrically conductive layer and the printed circuit board.
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申请公布号 |
US2012021599(A1) |
申请公布日期 |
2012.01.26 |
申请号 |
US201113252632 |
申请日期 |
2011.10.04 |
申请人 |
HALL JEFFREY;NIKOUKARY SHAWN;AMIN AMAR;JENKINS MICHAEL;LSI CORPORATION |
发明人 |
HALL JEFFREY;NIKOUKARY SHAWN;AMIN AMAR;JENKINS MICHAEL |
分类号 |
H01L21/60 |
主分类号 |
H01L21/60 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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